The present invention relates to integrated circuit design. More particularly, embodiments of the present invention relate to a method for performing a design rule check (DRC) on a layout design.
As integrated circuit (IC) technology advances, the complexity of IC designs increases, there is a need to satisfy the increase in design restrictions. In some cases, the design constraints are very strict, for example, in order to satisfy the performance requirements of a conventional layout design method, the layout of each pattern should be on grid. The term “on-grid pattern” means a pattern having the boundaries or edges arranged on the grid lines. Conversely, the term “off-grid pattern” means a pattern having the boundaries or edges not arranged on the grid lines. FIGS. 1A-1C show examples of layout patterns that are on-grid in the related art. These patterns may be portions of an IC layout and have polygonal shapes with boundaries (edges) arranged on the grid lines. The grid lines are shown as vertical lines 111 and have a grid interval (e.g., horizontal space 112) between them, as shown in FIGS. 1A-1C.
Under normal circumstances, when performing a design rule check on a layout design, the boundaries (edges) of each layout pattern of the layout design must be on-grid, otherwise off-grid errors will show up as the result of the DRC verification, and correction will be made to the off-grid boundaries (i.e., edges that are not arranged on the grid lines) to bring them back to on-grid.
However, as IC technology advances, on-grid layout patterns (i.e., all boundaries or edges of the layout patterns are on-grid) are not being able to satisfy the demand for the speed requirements of advanced technology devices. In some cases, off-grid layout patterns (i.e., at least a portion of the layout pattern is off-grid) may be required to ensure the device performance. FIGS. 2A-2D show examples of off-grid layout patterns having vertical edges 122 not arranged on the grid lines 111.
The current layout practice is to reduce the unit size (grid interval) of the grid to the next smaller size, for example, the 5 nm grid interval is reduced to 1 nm to satisfy the actual design layout requirements, i.e., the requirement of a particular pattern is satisfied and no off-grid errors will occur when running the DRC verification. However, this method only allows a limited number of specific patterns to be off-grid, and most of the layout patterns are to be on-grid.
For conventional off-grid layout designs, if a DRC verification is performed using an existing on-grid DRC deck, off-grid errors will occur. The term DRC deck means a computer file that contains DRC rules. Thus, there is a need to perform the DRC verification on off-grid patterns using an existing on-grid DRC deck without causing occurrence of off-grid errors.